In performing their various functions, processors have the need to provide and retrieve information to and from a system memory. Such information may include, for example, a program variable, instruction code, or peripheral data stored in the system's main memory. The processor reads the information from the system memory, executes one or more processes, and provides an appropriate output. In processing systems today, getting data in and out of system memory is time intensive. Furthermore, when a processor is waiting for data to be brought in, it is effectively stalled. One means known today for addressing this problem is the direct memory access (DMA) engine. The DMA engine is a hardware component that will obtain data from peripheral devices (known as peripheral data, or simply I/O data) and put that data into the main memory so that the processor itself does not need to execute a software subroutine to perform that task itself. However, when the DMA engine accesses the main memory, the processor must wait for the DMA engine to complete it's access before it can proceed with accessing the memory. If the processor needs program data or instruction code from the main memory to continue its processing at the same time the DMA is using the system memory, the processor must wait. This delay is commonly referred to in the art at “cycle stealing” because the DMA engine “steals” access to the memory from the processor for several cycles while the processor sits idle. Another means known today for improving processor throughput is commonly referred to as the “Harvard Architecture” that allows the processor to access memory via separate data and instruction ports. While this allows the processor to read instructions and access program variables concurrently from the memory, it does not solve the problem of the processor having to wait to access I/O data from peripheral devices.
For the reasons stated above and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the specification, there is a need in the art for improved systems and methods for processor memory access.